create_clock -period 8.000 -name i_phy_rxc -waveform {2.000 6.000} [get_ports i_phy_rxc]
create_clock -period 8.000 -name i_phy_rxc_v -waveform {0.000 4.000}
set_input_delay -clock [get_clocks i_phy_rxc_v] -max 1.000 [get_ports {i_phy_rx_ctrl {i_phy_rxd[0]} {i_phy_rxd[1]} {i_phy_rxd[2]} {i_phy_rxd[3]}}]
set_input_delay -clock [get_clocks i_phy_rxc_v] -min -add_delay -1.000 [get_ports {i_phy_rx_ctrl {i_phy_rxd[0]} {i_phy_rxd[1]} {i_phy_rxd[2]} {i_phy_rxd[3]}}]
set_input_delay -clock [get_clocks i_phy_rxc_v] -clock_fall -min -1.000 [get_ports {i_phy_rx_ctrl {i_phy_rxd[0]} {i_phy_rxd[1]} {i_phy_rxd[2]} {i_phy_rxd[3]}}]
set_input_delay -clock [get_clocks i_phy_rxc_v] -clock_fall -max -add_delay 1.000 [get_ports {i_phy_rx_ctrl {i_phy_rxd[0]} {i_phy_rxd[1]} {i_phy_rxd[2]} {i_phy_rxd[3]}}]
create_generated_clock -name o_phy_txc -source [get_ports i_phy_rxc] -multiply_by 1 [get_ports o_phy_txc]
set_output_delay -clock [get_clocks o_phy_txc] -max 1.000 [get_ports {o_phy_tx_ctrl {o_phy_txd[0]} {o_phy_txd[1]} {o_phy_txd[2]} {o_phy_txd[3]}}]
set_output_delay -clock [get_clocks o_phy_txc] -min -1.000 [get_ports {o_phy_tx_ctrl {o_phy_txd[0]} {o_phy_txd[1]} {o_phy_txd[2]} {o_phy_txd[3]}}]
set_output_delay -clock [get_clocks o_phy_txc] -clock_fall -min -1.000 [get_ports {o_phy_tx_ctrl {o_phy_txd[0]} {o_phy_txd[1]} {o_phy_txd[2]} {o_phy_txd[3]}}]
set_output_delay -clock [get_clocks o_phy_txc] -clock_fall -max -add_delay 1.000 [get_ports {o_phy_tx_ctrl {o_phy_txd[0]} {o_phy_txd[1]} {o_phy_txd[2]} {o_phy_txd[3]}}]

set_clock_groups -name asy_clk -asynchronous -group [get_clocks -of_objects [get_pins clk_gen_inst/inst/mmcm_adv_inst/CLKOUT0]] -group [get_clocks i_phy_rxc] -group [get_clocks i_phy_rxc_v] -group [get_clocks o_phy_txc]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_125m]
